The present invention relates to a power transistor with improved resistance to direct secondary breakdown.
As is known, one of the main reasons of failure in bipolar power transistors is the secondary breakdown. This normally destructive phenomenon limits the performance of these transistors, so that during the design particular care must be taken to avoid the possibility of occurrence of this phenomenon.
The nature of this instability is thermal and constitutes the main obstacle to the achievement of larger safe operating areas in bipolar transistors.
In order to improve the ability of transistors to withstand such stresses, several solutions have already been proposed. In particular, one solution provides the use of so-called ballast resistors, in series to the emitter of each elementary transistor, while the U.K. patent No. 1,467,612 discloses replacing each elementary transistor with a pair of transistors geometrically arranged so as to obtain a compensation of the thermal imabalances, and in the Italian patent application No. 21 028 A/84 filed in the name of the assignee of the present application each elementary transistor is controlled by an own current source so as to reduce electrothermic regeneration phenomena. Such known solutions, though allowing an improvement with respect to previous devices, however allow to reduce only partially the phenomenon of direct secondary breakdown and are not always free from disadvantages.
A more substantial improvement is achieved according to the solution in U.S. Pat. No. 4,682,197 assigned to the assignee of the present application. According to this solution, the power device consists of a plurality of elementary transistors electrically connected but physically spaced apart by an amount equal to 17 mils. In this manner the overall power transistor is capable of delivering a power equal to the sum of the powers related to the individual elementary transistors (cells, or "fingers", the latter term indicating a group of cells). However, the bulk is penalizing and, on the other hand, the solutions indicated in order to minimize the area occupied by the device, such as the insertion, between two adjacent elementary transistors, of drive transistors operating as current sources or of the elementary transistors of the complementary stage, if the device constitutes a class-B output stage, in which the two output transistors operate alternately, are limited in their usefulness, in particular when two metal layers cannot be used.